Electro-static discharge (ESD) protection circuits have been utilized in ASIC environments for some time. These circuits protect the core circuitry of an integrated circuit from ESD events that may cause damage to the core circuitry. FIG. 1 illustrates a prior art ESD protection circuit 100 including a clamping device 105 between a first power supply 110 (e.g., Vdd) and a second power supply 115 (e.g., ground). Clamping device 105 is driven by a set of inverters, each inverter including a pair of transistors 120/125, 130/135, and 140/145. The inverters are triggered by an RC network, which in this example includes a diode connected transistor 150 as a resistor and a capacitor 155.
Current ESD protection circuits, such as circuit 100, suffer from current leakage at a level that has not been a serious problem in the ASIC, but that has a clearly undesirable impact on certain applications that require very low current leakage. Typical applications with low current leakage requirements include, but are not limited to, image processing chips, wireless communication chips, mobile application chips, and low power applications. The RC triggers of many ESD protection circuits have particular problems with current leakage across their capacitors. Additionally, many of today's applications require smaller and smaller chips. The capacitors of RC triggers can take up significant space on a chip that otherwise could be utilized for other functional purposes. RC triggers in ESD protection circuits are also tuned to activate based on a predetermined RC frequency response. This frequency response may be undesirable in certain applications, particularly applications involving radio frequency (e.g., cellular communications chips). An improved ESD protection circuit with lowered current leakage is desirable.